首页 » VHDL代写 » VHDL代写 | Ensc 252-1204 Lab Assignment 04

VHDL代写 | Ensc 252-1204 Lab Assignment 04

这个作业是根据同步逻辑和计数器主题设计闹钟
Ensc 252-1204 Lab Assignment 04
Purpose of Lab Assignment 04 (LA04) is to design an alarm clock based on the synchronous logic and
counter topics we have learned during our lectures. The alarm clock will display the time, incrementing its
minutes on every clock pulse. When the alarm is set and the clock’s current time matches the alarm, the alarm
will ring (asserted signal) until dismissed. This assignment consists of the following tasks:
1) Designing a 4bit Register
2) Building counter (increment) circuits with a programmable maximums.
3) Building a counter chain, consisting of interconnected counter circuits. This chain effectively
implements a 24-hour counter for our alarm clock
For each design above, you will verify correct functionality using Quartus’ waveform editor.
4) In the final part of this lab, you will create a circuit which sets an alarm, and constantly matches the
current time to the set alarm. When a match occurs, the clock rings until dismissed. Functionality will be
verified through functional waveform simulations using Quartus.
You will require a good grasp of lecture 08 and lecture 10 to complete this lab.
This is an individual assignment.
D flip-flop Design:
• Use Quartus to make a new project called alarm_clockxxxx. (where xxxx are the last four
digits of your students number) . Ensure you specify the FPGA as Cyclone IV E, device
EP4CE115F29C7
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE Ieee.numeric_std.all;
ENTITY Registerxxxx IS
PORT( Clk : IN STD_LOGIC;
D : IN UNSIGNED(3 DOWNTO 0);
Q : OUT UNSIGNED(3 DOWNTO 0));
END Registerxxxx;
ARCHITECTURE Behaviour of Registerxxxx is
–You fill in the rest
END Behaviour;
Part 1:
• Use the code above as a template for entering the basic information to create your 4bit register
circuit.
• Write the ARCHITECTURE. Refer to your lecture notes for the behaviour of a register, noting that
a register is simply an n-bit flip-flop. Apply concepts in our lecture to create a 4bit unsigned version
of the flip-flop (aka register). Recall that input D will pass through to Q only on a rising edge
(transparent mode), else the circuit remains in opaque mode.
• Run an error check to catch any errors. Note that error checking and basic steps you should be taking
by default will no longer be mentioned in ENSC252 labs from here on in.
• For this lab, you may use Quartus waveforms (wvf) to verify the correct behaviour of your circuit
using functional simulation, for each part. Ensure the waveforms are included in your final report.
Lab Assignment 04 due Mon June 29th 2020 @11:59pm LA04 LA04

Part 2:
A) Counter circuit – version 1:
File > New > VHDL file, named counter1xxxx.vhd. Set this file as your Top-Level ENTITY
• Declare an ENTITY named counter1xxxx, with three 1bit input ports (ld, clk and rst), one 1bit output
flag, and one 4bit UNSIGNED output (cnt) as provided below.
• The counter circuit contains active high, synchronous logic (incl reset and load). It contains a count
register, and number of Flags (NoF) register with several muxes interconnected as follows:
• Upon a rising edge, Counter1xxxx a) retains its “count” register value if ld=0 & rst=0, b) resets the
“count” register contents if rst=1, or 3) increments the “count” register contents if ld=1, rst = 0 and the
total number of flags (NoF) asserted has reached the threshold numFlags.
• The numFlags threshold will require another accumulator in the ARCHITECTURE which tallies the
incoming ld signals, and places this accumulated value in a NoF register(can be implemented using a
signal too). This value will be compared during every incoming asserted load, and when the number of
flags has reached numFlags, the count register may increment and the NoF counter reset.
• The count register latches the value output by a saturated counter upon every rising edge. The
saturated counter counts to N, the generic number passed to the circuit as seen in the ENTITY above.
The term saturated counter refers to a circuit that increments from 0:N, and back to zero once the value
N is reached. In our case, the value of the counter register will only increment when the numFlags
threshold has been reached.
Note on assigning “N” to the 0:N increment circuit:
Consider a 24-hour clock aka military time, and the manner which minutes and hours are incremented per
digit position. Illustrated to the right is an example of the maximum count per hour and minute position
considering the 24-hour clock (00:00 -> 23:59):
Accordingly, our clock will increment as follows:
0:00 – 00:59
01:00 – 01:59
09:00 – 09:59
10:00 – 10:59
..
19:00 – 19:59
20:00 – 20:59 …
23:00 – 23:59 and back to 00:00
• The digit positions at min[0], min[1], and hr[1] consistently increment from zero to one maximum
value, N, shown here.
• The digit position at hr[0] increments interchangeably from zero to two different values. Specifically
from N (9) to N(9) and then N2 (3), back to N(9), N(9), N2(3)…. Etc. We will create another counter2
for this requirement.
hr[1] min[1] min[0]
hr[0]
ENTITY counter1xxxx IS
generic( N : integer := 9; numFlags : INTEGER := 2);
PORT(clk, rst, ld : IN STD_LOGIC;
count : OUT UNSIGNED(3 DOWNTO 0);
flag : OUT STD_LOGIC);
END counter1xxxx;
Lab Assignment 04 due Mon June 29th 2020 @11:59pm LA04 LA04

To make our counter1xxxx circuit applicable for all clock digit positions that increment from zero to a
maximum number, N, we will use a generic statement to assign the value of N. Integrate a generic
statement in your VHDL, and design the behaviour of the circuit to abide by the following if NoF =
numFlags (else previous value is retained):
• If the counter register value will equal N when incremented on the clock’s rising edge, assert the flag=1
and increment the counter to N. Hint: use the numeric_std library, unsigned type and “+ 1” syntax to
increment
• If the counter’s value will be less than N when incremented on the clock’s rising edge, increment the
counter circuit by 1, and flag = 0
• If the counter’s value will be greater than N if incremented on the clock’s rising edge, reset the counter
to zero. Flag = 0. NOTE: ensure that the flag is only asserted for one clock cycle, then unasserted
the next.
Since we are implementing sequential logic, you will have to code the VHDL by thinking 1) concurrently
and 2) in terms of what signals should be asserted for the next clock cycle.
The flag output of the min[0] circuit will be connected to all its left neighbour’s counter ld signal. This will
allow all of the counters to synchronize accordingly.
• Write the ARCHITECTURE for counter1, considering the description provided. All 4bit signals
required are also of type UNSIGNED. You may implement the code in various ways, the easiest being
the following: Use one process with nested conditional statements to implement the entire circuit. In
this case, you may or may not want to use the 4bit register circuit from the previous stage. You must
integrate the functionality of the 0:N increment circuit and number of flags accumulator as well.
Hint: Verify that Your circuit is working correctly using a functional simulation. Thoroughly test all the
possibilities, ensuring that your circuit implements 0:N saturated increment functionality, flags are asserted
and unasserted as required based on N and numFlags, and that all ld and reset input combinations work as
intended. You may find it helpful to use Modelsim so that you can extract additional internal signals for
debugging.
B) Counter circuit – version 2 (counter2):
• File > New > VHDL file, named counter2xxxx.vhd. Set this file as your Top-Level ENTITY
• Declare an ENTITY named counter2xxxx. The ENTITY is identical to that of counter1, however now
with two generic parameters, N and N2 and two numFlags(1 and 2). The rest of the ENTITY remains the
same i.e. three 1bit input ports (ld, clk and rst), one 1bit output flag, and one 4bit UNSIGNED output
(cnt).
• Re-implement your ARCHITECTURE such that you now have the possibility to increment to two
maximum thresholds, where the counters are activated in the sequence N, N, N2. That is, you would now
like to increment 0:N, assert the flag out for a clock cycle, increment to N once again, assert the flag, and
then activate the circuit to increment from 0:N2. The counter is only incremented if its associated
numFlags is reached, as outlined on the previous page.
• Once the counter has incremented to N2, it asserts the flag for one clock cycle, while passing control back
to the 1st counter sequence, which starts incrementing from 0:N twice, then 0:N2 etc. Consider hour[0] in
the diagram on the previous page.
• Hint: You may implement internal signals to determine when to activate a given counter, or even use a
state machine to go from one state to another, activating the appropriate counter after a flag has been
asserted.
Part
2B:
Lab Assignment 04 due Mon June 29th 2020 @11:59pm LA04 LA04

Counter Chain circuit:
File > New > VHDL file, named Counter_chain.vhd. Set this file as your Top-Level ENTITY
Part 3:
• In counter_chain.vhd, declare an ENTITY named counter_chain, with the ports named as shown in the
diagram below.
• Use the structural diagram shown here as a template for designing your counter chain circuit
• Label internal signals, instances and ports. Design the system ARCHITECTURE in VHDL based on
the structural diagram. Determine the appropriate values to each of the components generic map
variables, based on their position in the 24-hour clock.
• Hint: Check that the circuit is connected correctly using the RTL viewer.
• Verify that the circuit is correct using a waveform that exhaustively tests the system. Ensure that the clock
properly counts from 00:00 -> 23:59
• Note that Vdd input connections imply connecting the given port to a constant ‘1’ (therefore ground
inputs signify a constant ‘0’), and outputs connected to ground may be mapped as null or open
• Verify that your counter2xxxx circuit is working correctly using a functional simulation. Thoroughly
test all the possibilities, ensuring that your circuit alternates counts give an N, N and N2 input according
to the numFlag1 and 2 variables, which tally the incoming loads. Verify that flags are asserted and
unasserted as required, and that all ld and reset input combinations work as intended.
• At this point you will notice that the most significant bit, located at digit 3 does not work as
intended. That is, it does count from 0 to 2, but it does not terminate once we reach 23:59
• What’s the issue? if we program the counter with just one generic numFlag and one generic N input, the
load assertion counts required of 00:00 – 09:59, and 10:00 – 19:59 are not the same as the numFlags
required of 20:00 – 23:59.
• Accordingly, we will create another counter with the following ENTITY, called counter3xxxx
Copy the functionality implemented in counter1xxxx and add the following behaviour: When the counter is < N, numFlags1 will be used as the threshold for load assertions, incrementing the counter when the threshold is met. When counter = N, the circuit will start counting the number of load assertions to a max threshold of numFlags2 instead. Replace count(?) above with counter3xxxx. Verify that the counter works as expected first. You will be submitting all these waveforms for functionality verification count1 ld cnt flag rst count1 ld cnt flag rst count(?) ld cnt flag rst count2 ld cnt flag rst reset clock digit3 digit2 digit1 digit0 4 4 4 4 Vdd counter_chain count1 ld cnt flag rst count1 ld cnt flag rst count(?) ld cnt flag rst count2 ld cnt flag rst reset clock digit3 digit2 digit1 digit0 4 4 4 4 Vdd counter_chain ENTITY counter3 IS generic( N : integer := 9; numFlags : INTEGER := 2; numFlags2 : INTEGER := 2); PORT(clk, rst, ld : IN STD_LOGIC; count : OUT UNSIGNED(3 DOWNTO 0); flag : OUT STD_LOGIC); --this should be called flag END counter3; Lab Assignment 04 due Mon June 29th 2020 @11:59pm LA04 LA04 Part 4: Alarm Clock Design: A) set alarm functionality Alarm Clock Design: B) Integrating all components • Create a new VHDL file, named alarm_clock.vhd. Set this file as your Top-Level ENTITY • In alarm_clock.vhd, declare an ENTITY named alarm_clock, with the given input and output ports as shown in the diagram provided on the next page. Feel free to name the input/output ports as you wish. Connect signals appropriately from component to the top-level ENTITY. • Add the counter_chain, set_alarm components to your ARCHITECTURE using the structural diagram. Assume that the SevenSeg (and display_hex) will be added to your testbench. Therefore, integration of the displays are not needed in your alarm_clock ARCHITECTURE. • It is a good idea to label all your signals and instances before proceeding to port map your design in alarm_clock.vhd • Once you have connected all components appropriately, create a waveform which thoroughly tests alarm_clock using the Quartus wvf method. Note sevenSeg/disp_hex are not necessary; they are used for illustrative purposes. You may find it useful to use the “clock” button in Quartus to generate clock like pulses in the waveform to save time. Set the output ports to decimal Radix to ease testing: right-click the signal > Radix > Unsigned Decimal
• Ensure all alarm set, dismiss, and clock counts function correctly. Ensure to extract the signals prior
to the connection to SevenSeg in order to easily verify correctness. The seven segment displays have
been added for the sake of a completeness given this remote semester.
• Design the system ARCHITECTURE in VHDL based on the structural diagram on the next page
• Create a new VHDL file, named set_alarmxxxx.vhd. Set this file as your Top-Level ENTITY
• In set_alarm.vhd, declare an ENTITY named set_alarmxxxx, with the ports named as shown in the
diagram below: 8 4bit UNSIGNED inputs, two 1bit inputs dismiss and set, and one 1bit output, ring.
• Next, you will need to implement the alarm clock functionality:
• The four 4bit inputs alarm correspond to the alarm time the user would like to set, where alarm3 is
the most significant bit, and alarm0 the least significant bit. The alarm is set internally when the “set”
signal is asserted, with the corresponding values for alarm[3:0] simultaneously applied to the input.
Thus if a user changes their mind and would like to set the alarm to another time, they may assert
“set” once again while simultaneously applying the new alarm[3:0] time to the input.
set_alarm
ring
4 alarm0
4 alarm1
4 alarm2
4 alarm3
4 cnt0
4
4
cnt1
cnt2
cnt3
4
dismiss
set
set_alarm
ring
4 alarm0
4 alarm1
4 alarm2
4 alarm3
4 cnt0
4
4
cnt1
cnt2
cnt3
4
dismiss
set
• To make our circuit simple, there is no way to cancel the alarm, other than
to dismiss the alarm once it has rang.
• The cnt[3:0] input signals will be connected to the outputs of the count
circuits implemented in Part 3. When cnt[3:0] matches the set alarm[3:0],
the ring signal is asserted.
• The set_alarm circuit then awaits for the dismiss signal input to be ‘1’
before unasserting its “ring” output.
• Based on the specified description for the set_alarm circuit, create the
corresponding ARCHITECTURE for the circuit. Use any internal signals
as required (i.e. to retain the set alarm time, for instance) .
• Test for correct functionality of all possible scenarios using a functional
waveform (wvf) in Quartus.
Lab Assignment 04 due Mon June 29th 2020 @11:59pm LA04 LA04

• You can screenshot or print the waveforms as a pdf, and include it in the Visio file. You can also prepare
an image of the waveforms using the snipping tool available on the windows start menu under
accessories. For each waveform:
• Add a textbox in Visio to Title the simulation results..
• Add a textbox in Visio – enter a brief discussion about the simulation results.
• Using lines and textboxes, annotate the image to highlight important features of your simulations.
• Submit functional waveforms for all your designs.
Prepare All Design Source-Code for Submission:
• Insert new pages in your visio document, one for each VHDL file and waveform created in this lab.
Ensure that they are ordered in accordance with the lab (i.e. Part1 4bit register, Part2 counter…. Part 4,
final alarm_clock)
• Copy/Paste each VHDL source-code with syntax highlighting into the visio file. Change the font to
COURIER NEW(a non-proportional font that maintains correct code alignment). See suggestions and
directions from your previous labs.
• Within your VHDL file in Quartus, add your own comments. Your comments can be anywhere in the
files and are for YOUR benefit.
• Add a textbox to Title each source code.
Prepare Waveforms for Submission:
• As the case with your previous waveforms, try some experiments to produce a GOOD view of the
waves. The symbols should be clear to read and the window should not waste paper with empty space.
Adjust the height of the waves so that it is easy to distinguish between the rows. Ensure all necessary
waveforms are included for each part of this lab
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count2
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count2
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count2
ld
cnt
flag
rst
reset
clock
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count2
ld
cnt
flag
rst
reset
clock
digit3 digit2 digit1 digit0
4 4 4 4 Vdd
counter_chain
7Seg 7Seg 7Seg 7Seg 7Seg 7Seg 7Seg
set_alarm
ring
alarm0
4
alarm3
alarm2
alarm1
cnt3
cnt2
cnt1
cnt0
set
dismiss
4
4
4
4
4
4
4
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count2
ld
cnt
flag
rst
reset
clock
digit3 digit2 digit1 digit0
4 4 4 4 Vdd
counter_chain
7Seg 7Seg 7Seg 7Seg
set_alarm
ring
alarm0
4
alarm3
alarm2
alarm1
cnt3
cnt2
cnt1
cnt0
set
dismiss
4
4
4
4
4
4
4
alarm_clock
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count1
ld
cnt
flag
rst
count2
ld
cnt
flag
rst
reset
clock
digit3 digit2 digit1 digit0
4 4 4 4 Vdd
counter_chain
7Seg 7Seg 7Seg 7Seg
set_alarm
ring
alarm0
4
alarm3
alarm2
alarm1
cnt3
cnt2
cnt1
cnt0
set
dismiss
4
4
4
4
4
4
4
alarm_clock
Lab Assignment 04 due Mon June 29th 2020 @11:59pm LA04 LA04

Prepare Full Document for Submission:
• Complete the cover page. Use the template provided on Canvas, and change any necessary field for this
lab assignment.
• Check that the document contains the items specified for submission, as indicated throughout this lab.
• Insert a discussion into the document, wherever appropriate, detailing the purpose of the circuit
and the expected/achieved functionality.
• Save the visio file as a PDF file. Make sure that the filename is LA04-252-1204-xxxx.pdf, (using the
last 4 digits of your student number as usual).
• Include all your Quartus projects within a single folder, zip the folder with the pdf report included.
Therefore, when unzipping the file, the TA should see a 1) folder containing your Quartus project, and 2)
your report as a pdf.
• upload your .zip file to Canvas, entitled LA04-252-1204-xxxx.zip .
• Don’t forget to signup for your demo. See semester schedule and calendar
Part 5:


程序辅导定制C/C++/JAVA/安卓/PYTHON/留学生/PHP/APP开发/MATLAB


本网站支持 Alipay WeChatPay PayPal等支付方式

E-mail: vipdue@outlook.com  微信号:vipnxx


如果您使用手机请先保存二维码,微信识别。如果用电脑,直接掏出手机果断扫描。

标签:

发表评论

电子邮件地址不会被公开。 必填项已用*标注