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VHDL代写 | Advanced Digital Design Module code: ENGD3001

这个assignment是用VHDL完成电路仿真设计
Assignment 2 Coursework Specification
Module name: Advanced Digital Design
Module code: ENGD3001
Title of the Assignment: Assignment 2
This coursework item is: Formative
This coursework will be marked anonymously: Yes
The module learning outcomes that are assessed by this coursework are:
1. “Knowledge and specialist analytic development techniques in the areas of VLSI design, ASM design
and implementation, and VHDL design.”
2. “Development of generic and transferable skills in advanced digital system design methodologies using
industry standard design tools.”
This coursework is: Individual
This coursework constitutes 24% to the overall module mark.
Date Set: Week 21 (17 Feb 2020)
Date & Time Due: Week 27 (by 4:00 PM on Friday, 3 April 2020)
When completed you are required to submit both of the following:
1. Submit a printed copy of your assignment to the Faculty of Computing, Engineering & Media
Student Advice Centre (CEMAC) in the Gateway House by the advertised deadline.
2. Submit an electronic copy of your assignment to TURNITIN via Blackboard by the advertised
deadline.
 IMPORTANT: Partial submissions are not acceptable. Failure to submit both the
hardcopy to FOTAC and the electronic copy to Turnitin amounts to a non-submission.
Your marked coursework and feedback will be available to you on:
If for any reason this is not forthcoming by the due date your module leader will let you
know why and when it can be expected. 7 May 2020
Late submission of coursework policy:
Late submissions will be processed in accordance with current University regulations which state:
“The time period during which a student may submit a piece of work late without authorisation and have the
work capped at 40% [50% at PG level] if passed is 14 calendar days. Work submitted unauthorised more
than 14 calendar days after the original submission date will receive a mark of 0%. These regulations
apply to a student’s first attempt at coursework. Work submitted late without authorisation which constitutes
reassessment of a previously failed piece of coursework will always receive a mark of 0%.”
Academic Offences and Bad Academic Practices:
These include plagiarism, cheating, collusion, copying work and reuse of your own work, poor referencing or
the passing off of somebody else’s ideas as your own. If you are in any doubt about what constitutes an
academic offence or bad academic practice you must check with your tutor. Further information and details of
how DSU can support you, if needed, is available at:
http://www.dmu.ac.uk/dmu-students/the-student-gateway/academic-support-office/academic-offences.aspx
and
http://www.dmu.ac.uk/dmu-students/the-student-gateway/academic-support-office/bad-academic-practice.aspx
Module leader/tutor name: Dr Cristian Serdean
Contact details: Email: cvs@dmu.ac.uk
Phone: 0116 207 8400 (ext. 8400)
Assignment 2
The figure below shows the state transition diagram of a finite state machine (FSM). This diagram
shows the input conditions which initiate the necessary transitions. If no input condition is satisfied,
then the FSM remains in the same state.
The outputs of the FSM are defined in the following table:
Implement this FSM in VHDL and simulate its behaviour with the aid of a text-based testbench (a
testbench written in VHDL). Please ensure that you design your testbench in such a way that it
verifies all possible states/transitions from the above diagram.
What you should submit
You should submit a formal report explaining your design and your results. For general guidance on
writing (technical) reports please refer to the following links:
https://www.theiet.org/media/5182/technical-report-writing.pdf
https://library.dmu.ac.uk//ld.php?content_id=1879519
https://library.dmu.ac.uk/class/HEAT.
Specifically, your report should contain at least: a) an introduction, including the design brief, b) a
background section, c) a section explaining how you’ve solved the design task handed out to you and
if applicable why you’ve selected a particular solution out of several possible, d) the complete listing
of the VHDL code for the FSM and for the testbench, bearing in mind good programming and
design practice, e) the results of the simulations (i.e. suitable, legible and detailed simulation
waveforms) accompanied by detailed comments and explanations, and f) conclusions (and possible
further improvements if applicable). Avoid including simulation waveforms with a black background.
For full marking details please consult the associated marking scheme on Blackboard.
Please also make sure that you read the corresponding Blackboard announcement and the
ENGD3001 “module handbook” (pg.7-10) which contain important information, advice and
guidelines regarding your assignments.


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