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Verilog代写 | CS4100 Computer Architecture Homework 4-1: Single-cycle CPU

这个作业是用Verilog实现一个简单的单周期RISC-V
CS4100 Computer Architecture
Homework 4-1: Single-cycle CPU
Due: 23:59, 6/2 2020
1. Introduction
A central processing unit (CPU), also called a central processor or main processor,
executes instructions that make up a computer program. A single-cycle CPU executes
only one instruction in a clock cycle, and the execution contains instruction fetching,
instruction decoding, arithmetic/logic operations and communications with registers
and memory.
In this homework, you are asked to implement a simple single-cycle RISC-V
processor with the given structure shown below.
2. Problem Description
(1) Architecture
(2) Input:
A sequence of instructions in binary is given as the input. The instruction set
contains ADD, SUB, AND, OR, SLT, SLTI, ADDI, LD, SD and BEQ.
Assembly code Machine code
ADD 0000000 rs2 rs1 000 rd 0110011
SUB 0100000 rs2 rs1 000 rd 0110011
AND 0000000 rs2 rs1 111 rd 0110011
OR 0000000 rs2 rs1 110 rd 0110011
SLT 0000000 rs2 rs1 010 rd 0110011
SLTI immediate[11:0] rs1 010 rd 0010011
ADDI immediate[11:0] rs1 000 rd 0010011
LD immediate[11:0] rs1 011 rd 0000011
SD imm[11:5] rs2 rs1 011 imm[4:0] 0100011
BEQ imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011
(2) Predefined files (do NOT modify them):
The files below are given to you, but you don’t need to hand them in. TAs
will use the default version to verify your implementation’s correctness. In other
words, any modification will NOT take effect.
1. Makefile
2. Instr_Mem.v
3. Reg_File.v
(3) Predefined files (TODO):
The files below are templates. Their input and output ports are predefined,
and what you have to finish are the computations in each module and the
connections among the modules.
1. Adder.v 2. ALU.v
3. ALU_Ctrl.v 4. Control.v
5. Data_Mem.v 6. MUX_2to1.v
7. Program_Counter.v 8. Shift_Left_One_64.v
9. Imm_Gen.v 10. Simple_Single_CPU.v (top
module)
(4) Output and testbench:
By using makefile to run all your Verilog files with testbench.v, the
console will show all the registers’ values in the end.
The usage of makefile and the manual of the workstation environment
setup are provided in other pdf files.
3. Language/Platform
(1) Language: Verilog
(2) Platform: Unix/Linux
4. Required Items
Do NOT compress your files! Please upload the 10 .v files (TODO) to iLMS.
1. Adder.v 2. ALU.v
3. ALU_Ctrl.v 4. Control.v
5. Data_Mem.v 6. MUX_2to1.v
7. Program_Counter.v 8. Shift_Left_One_64.v
9. Imm_Gen.v 10. Simple_Single_CPU.v (top
module)
Do NOT add/modify any clock or rst settings in your Verilog code, for example,
#delay.
Do NOT modify any filename.
Do NOT use $stop in your Verilog code.
Any violations will cause strong penalties!
5. Grading
 60%: Public testcases. Note that you will get 60 points if you pass all the public
testcases; however, if you fail in any of them, you will NOT get any points. In
short, please make sure your Verilog code’s correctness in the public testcases.
 40%: Hidden testcases.
※ (Final score) * 0.9: Any interruption during the simulation.
※ (Final score) = 0: Plagiarism. We encourage the discussions on the architecture
or the data flow rather than code. Don’t read others’ code before you finish
yours!


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