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Cs代考 | ELEN30010 (DSD) Exam

本次澳洲代考主要为verilog数字系统设计限时测试

Question 1.1 (12 marks)
Draw the state transition diagram for the following Moore Finite-State Machine (FSM). Use only five
states. Give the states meaningful names (not numbers).
The FSM has 3 output bits, labelled R, G and B. (You can think of these as connected to three LEDs, a
Red, a Green and a Blue LED.)
The FSM has 2 input bits, with the following meaning.
00 – the output is 000 (all LEDs off).
01 – the output cycles repeatedly, first 100 then 010 then 001, then back to 100 then 010 then 001
and so forth (the LEDs will repeatedly light up in the order red then green then blue).
10 – the output cycles repeatedly in the opposite direction: first 001 then 010 then 100, then back to
the beginning, so 001 then 010 then 100 again, and so forth (the LEDs will repeatedly light up in the
order blue then green then red).
11 – the output is 111 (all LEDs on).

Question 1.2 (12 marks)
Implement in Verilog the FSM in Question 1.1, in canonical form (as taught in lectures). Use
localparam to give numbers to the states, using the naming convention you chose in your answer to
Question 1.1. Explicitly initialise the FSM to the state having the output of 3’b000. Use exactly the
following module definition: module MyFSM(input clk, input [1:0] in, output [2:0] out);
Use assign statements to determine each bit of the output, as in: assign out[0] = …; assign out[1] =
…; assign out[2] = …;
Use casex({state,in}) for the transition logic.

Write down the output of the following Verilog code.
module Jiayou;
initial #10 $display(“Hello!”);
reg clk = 0;
initial repeat (12) #1 clk = !clk;
reg signed [3:0] x = 0;
always @(posedge clk) begin
x <= x + 3;
$display(“Time = %2d, x = %2d”, $time, x);
end
endmodule


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