(1) Compute the effective access time, in seconds, of a memory system consisting of a cache and main
memory with a processor running at 2GHz. The cache hit time is one cycle. The miss penalty is 55
cycles. The hit rate is 94%.
(2) Compute the total number of bits of storage required to implement a cache that is similar to the cache
shown in Figure 5.18 on page 426, except that the associativity of the cache is 8instead of 4. All the
other parameters (cache size, block size) are the same as in Figure 5.18. Note that the number you are
being asked to compute is different from the ‘‘size of the cache, ’’ which refers only to the number of
bits of data stored in the cache.
(3) A CPU generates 50 bit addresses. The memory system is word-addressable. The cache contains
8192 block frames. The tag size is 34 bits. Based on this information, what is the block size?Ifa
range of block sizes is possible, specify this range.
(4) 5.2.2 in the book. Note that the problem refers to a reference trace shown higher on the page
In addition to what is asked in the book, showthe ﬁnal contents of the cache. This means that, for
each block frame that contains a valid block, showthe block number,the word addresses of the words
in the block, and the tag of that block.
(5)-(7) 5.8.1, 5.8.2, 5.8.3
Note: The minimum addressable unit of the processor is a byte and the addresses shown in the
address stream are byte addresses.
(8) The minimum addressable unit of a memory system is a 32-bit word. The memory system includes a
four-way set-associative cache. The block size is eight words.
The data part of the cache is implemented using a single conventional 64K × 32 RAM chip. We
will call this chip C1.The connections to C1 are as shown on page 10.24 in the notes. Youcannot
modify C1 in anyway.
Foreach address generated by the CPU, the cache controller,using the directory part of the cache,
maps that address to an address in C1.
A) The CPU generates the address 0x321. This access is a hit in the cache. Specify the address in
C1 where the word is found. If more than one answer is possible for your assumed
implementation of the cache controller and directory,you must specify all possible answers.
B) Repeat part A for address 0x9876543.
(9) Consider the multicycle MIPS implementation described in Figure e4.5.4 (page 4.5-6), and Figure
e4.5.13 (page 4.5-20), of Section 4.5 in the textbook. This processor executes a program with the
following instruction mix:
loads 27% branches 20%
stores 13% jumps 2%
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