- Investigate the memory hierarchy of your computer. Identify the processor and the cache memory and the amount and type of DRAM in your main memory.
- Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The table shows data for L1 caches attached to each of two processors, Pl and P2.
a) Assuming that the Ll hit time determines the cycle times for Pl and P2, what are their respective clock rates?
b) What is the Average Memory Access Time for Pl and P2?
c) Assuming a base CPI of 1.0 without any memory stalls, what is the CPI for Pl and P2?
Which processor is faster?
- For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.
a) What is the cache block size (in words)?
b) How many entries does the cache have?
c) What is the ratio between total bits required for such a cache implementation over the data
Starting from power on, the following byte-addressed cache references are recorded.
d) How many blocks are replaced?
e) What is the hit ratio?
f) List the fifinal state of the cache, with each valid entry rep’d as a record of <index, tag, data>.
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