这是一篇美国的计算机组织代码代写
- Investigate the memory hierarchy of your computer. Identify the processor and the cache memory and the amount and type of DRAM in your main memory.
- Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The table shows data for L1 caches attached to each of two processors, Pl and P2.
a) Assuming that the Ll hit time determines the cycle times for Pl and P2, what are their respective clock rates?
b) What is the Average Memory Access Time for Pl and P2?
c) Assuming a base CPI of 1.0 without any memory stalls, what is the CPI for Pl and P2?
Which processor is faster?
- For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.
a) What is the cache block size (in words)?
b) How many entries does the cache have?
c) What is the ratio between total bits required for such a cache implementation over the data
storage bits?
Starting from power on, the following byte-addressed cache references are recorded.
d) How many blocks are replaced?
e) What is the hit ratio?
f) List the fifinal state of the cache, with each valid entry rep’d as a record of <index, tag, data>.
程序辅导定制C/C++/JAVA/安卓/PYTHON/留学生/PHP/APP开发/MATLAB
本网站支持 Alipay WeChatPay PayPal等支付方式
E-mail: vipdue@outlook.com 微信号:vipnxx
如果您使用手机请先保存二维码，微信识别。如果用电脑，直接掏出手机果断扫描。
