ELEC 385: Computer System Design
1. Problem Solving: Exercise 5.2 in the Textbook
Design two adders: a 64-bit ripple-carry adder and a 64-bit carry lookahead adder with 4-bit
blocks. Use only two-input gates. Each two-input gate is 15 μm2, has a 50 ps delay, and has
20 fF of total gate capacitance. You may assume that the static power is negligible.
(a) Compare the area, delay, and power of the adders (operating at 100 MHz and 1.2 V)
(b) Discuss the trade-offs between power, area, and delay
( Note: For power calculation use Equation 1.4):
Pdynamic = ½ CVDD 2 f
2. In Multisim connect a 4-bit adder (’283) and a 4-bit shift register (‘195) such that the adder
adds a 4- bit input to the contents ofthe register. Thatsum isto then be loaded into the register
when the register clock transitions from low to high. Use digital interactive inputs for the
input and the clock. Manually toggle the clock input and test your adder for several
increment inputs. The datasheets can be found on Brightspace. Submit only the circuit
3. Express (-5.46875)10 in the following number formats. Convert your answers to hex.
a) Sign and magnitude fixed-point format with six integer bits (including sign) and ten
b) IEEE 754 single precision floating-point format
4. Perform the following on IEEE 754 single-precision floating-point numbers. Express the
answers in hex.
a) 0xC1660000 + 0x431C0000
b) 0xC1660000 × 0x431C0000
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