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操作系统代写 | CS-UY 2114 | Spring 2020 — Assessment Activity 4

这个作业是回答操作系统有关的问题等
CS-UY 2114 | Spring 2020 — Assessment Activity 4
Due May 15, 2020, 11:55 PM (EDT)
Note: State your name and net ID on your submission. Individual Assessment
Attempt ALL questions. 20 points total
____
Instructions: For all questions, show your working. Both technical accuracy and presentation of your
answers will influence the mark you gain. Poorly presented answers (e.g., without the intermediate steps),
whilst otherwise correct, may not receive full marks. Write out equations you are using (e.g., for AMAT).
Assume all addresses are byte addresses
Question 1 [5 points]
Answer the following general questions about virtual memory systems:
(a) What are two of the benefits that are provided by using a virtual memory system? Explain them.
(b) Are there any issues with small page sizes? Why/Why not? What happens if we use very large
page sizes instead?
(c) Is it possible that a page, not in main memory, is also not found in secondary storage? Why/why
not?
(d) Given a 20-bit virtual address, 4 KiB pages, and 4 bytes per page table entry, what is the total page
table size?
(e) How many bits are required for the virtual page number when the virtual address space is 32 GiB,
and the page size is 16 KiB?
(f) A virtual memory system uses 4 KiB pages. With a TLB that contains 16 entries, what is the
memory coverage of the TLB?
(g) “Page faults are usually handled entirely by hardware to reduce the performance overhead.” Is this
statement true or false? Why?
(h) What is a translation lookaside buffer? What purpose does it serve? Can an entire page table be
stored in the translation lookaside buffer?
(i) A program requests data from the cache—it is a cache hit. Is it guaranteed that the entire page of
memory, from which the data is from, must be currently resident in the cache? Why/why not?
Question 2 [5 points]
Consider a virtual memory system that can address a total of 4 GiB. There is only 128 MiB of physical
memory. Assume that we use 4 KiB pages.
Answer the following:
(a) How many bits are used in the physical address?
(b) What is the maximum number of virtual pages?
(c) How many physical pages are there in the system?
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CS-UY 2214 (BT 2020)
Question 3 [5 points]
A processor uses a virtual memory system, with a TLB, as well as an L1 cache that is physically indexed
and physically tagged. Sketch and describe the steps involved when the processor attempts to write a
piece of data to memory, given that the memory location to be written to is currently in secondary
storage. The L1 cache uses a write-back policy, and it is currently fully occupied with dirty data. You will
need to describe which components are used, when the OS becomes involved, whether there are
hits/misses, if TLB entries are updated, if there are faults, etc.
Question 4 [5 points]
Consider a virtual memory system which uses a 32-bit virtual address. Each process has a Page Table that
consumes 1 MiB of memory. Each entry in a Page Table requires 4 bytes. In this system, 256 MiB of
physical memory is available.
Answer the following:
(a) How large is each virtual page in this system?
(b) For any given virtual page, what must be the size of the corresponding physical page? Why?
(c) How many physical pages can there be in the physical memory?
(d) Is it possible for a memory access to trigger a TLB miss even though the requested page is in main
memory? Why/why not?
______________________________
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